1. Field of the Invention
This invention relates to a data transfer apparatus which transfers data between a memory and an external I/O device, or between memories. In particular, this invention relates to a data transfer apparatus which transfers a series of data, including a plurality of words, at a high speed.
2. Description of the Prior Art
An example of a data transfer apparatus according to the prior art of the present invention is shown in FIG. 11. The apparatus shown in this figure is a DMA controller (Direct Memory Access Controller) which is used instead of a processor to control a data transfer.
As shown in FIG. 11, the prior art DMA controller 50 is comprised of the following: a data register DTR; a destination address register DAR; a source address register SAR; a byte count register BCR; an operation defining register ODR; a subtracter 53; adders 54 and 55; and a DMA control circuit 52.
DMA controller 50 executes a data transfer between a memory and an external I/O device, or between memories. In a practical way of data transfer, DMA controller 50 once stores transfer data into internal data register DTR. In this case, first, DMA controller 50 outputs the address of a device, from which data are transferred, onto address bus ABUS. Then, DMA controller 50 stores transfer data into internal data register DTR. These processes are referred to a read bus cycle. Next, DMA controller 50 executes a write bus cycle. In other words, DMA controller 50 outputs the address of a destination device onto address bus ABUS, and then, outputs the transfer data, stored in data register DTR, onto data bus DBUS so as to execute a data transfer.
In the prior art data transfer apparatus mentioned above, data register DTR in controller 50 has only one word capacity. Therefore, the memory access is carried out in a one word unit at a maximum.
Data register DTR is controlled by means of read signal RD#, write signal WR#, and timing signal LTC#, which are output from DMA control circuit 52. Read signal RD# becomes active when the transfer data are stored into the internal register, and write signal WR# becomes active when the transfer data are output from the internal register. Timing signal LTC# determines the timing for storing the transfer data into data register DTR. In those signals, ones having # show that they are negative logic signals, so that they become active when their states are low, that is, in level L.
FIG. 12 shows the transition of bus states. In this figure, state Ti means that DMA controller 50 is in an idle state instead of a bus master state. Also, state Ta means that it is the starting cycle of a DMA data transfer, and state Td means that it is a data transfer cycle of the DMA data transfer. One bus cycle is comprised of one state Ta and more than one state Tds.
Next, the operation to transfer four words from a memory to an external I/O device in one word (32 bits) unit will be described with referring to the timing chart shown in FIG. 13.
When a transfer request arises out of DMA controller 50 or the external I/O device, DMA controller 50 acquires a bus utility right from a processor and changes its state from state Ti to state Ta, thus starting a memory read cycle. Once state Ta has started, the address of the device from which data are transferred, (that is, the values stored in source address register SAR), is output onto address bus ABUS (signals A00.about.A29, and signals BC0# .about.BC3#). At the same time, read-write signal R/W# is set at level H, and bus start signal BS# is set at level L. Also, address strobe signal AS# is set at level L at the falling clock signal CLKin of state Ta.
In the following state Td, bus start signal BS# is set at level H and data strobe signal DS# is set at level L at the first rising of clock signal CLK. Also, data transfer end signal DC# is sampled at the falling of clock signal CLK in state Td. In this case, DMA control circuit 52 causes read signal RD# to change to level L, and write signal WR# to change to level H, in order to store the transfer data, which have been carried by data bus DBUS (signals D00 .about.D31), into data register DTR.
If data transfer end signal DC# being sampled is at level L, address strobe signal AS# and data strobe signal DS# are caused to change to level H. Adder 54, then, increases the number of source address register SAR by the byte number of transfer data (in this case, four bytes), in order to complete the memory read cycle. On the other hand, data transfer end signal DC# being sampled is at level H, this cycle should be considered to be a wait cycle, and so, state Td continues.
Once the memory read cycle has been completed, an I/O write cycle begins. When state Ta is started, the address of the device into which data are transferred, (that is, the values in destination address register DAR) is output on address bus ABUS. Also, read-write signal R/W# and DMA transfer response signal DACK# are set at level L. Address strobe signal AS# is set at level L at the falling of clock signal CLK in state Ta.
At the first rising of clock signal CLK in the next state Td, bus start signal BS# is set at level H and data strobe signal DS# is set at level L. Also, DMA control circuit 52 causes read signal RD# to change to level H and write signal WR# to change to level L in order to output the transfer data, which have been stored in data register DTR, onto data bus DBUS.
The sampling of data transfer end signal DC# is carried out at the falling of clock signal CLK in state Td. If data transfer end signal DC# being sampled is in level L, address strobe signal AS# and data strobe signal DS# are set at level H. At the same time, subtracter 53 decreases the values in byte count register BCR by the byte number of transfer data (in this case, four bytes) in order to complete the I/O write cycle. On the other hand, if data transfer end signal DC# being sampled is in level H, the present cycle is considered to be a wait cycle to continue state Td. If another transfer request is generated at the end of said I/O write cycle, state Ta starts next, allowing DMA controller 50 to repeat the data transfer described above. If no transfer request is generated, DMA controller 50 relinquishes the bus utility right and turns into state Ti.
Accordingly, in order to transfer one word data, the prior art DMA controller 50 requires at least four clocks, two of which are for state Ta and Td in one read bus cycle and the rest of which are for state Ta and Td in one write bus cycle. So, it requires 4.times.n clocks to transfer n word data.
As mentioned above, the prior art data transfer apparatus has a data register which has only one word capacity. As a result, the apparatus carries out a memory access only in a one word unit, at a maximum. This fact is disadvantageous in improving the speed of DMA data transfer.
For example, a dynamic RAM, which is a kind of memory, is accessible not only by a conventional access mode but by a high speed access mode, such as a page mode, as well. When an address is given in the high speed access mode, a series of data can be derived from the address being given. Therefore, the following data access can be executed at a high speed.
However, the prior art data transfer apparatus cannot make use of the high speed access mode of the memory mentioned above, because the apparatus does not have a function to deal with a series of data, having a plurality of words, at a time.